1. Field of the Invention
This invention relates generally to voltage booster circuits. More particularly, it relates to an improved voltage booster circuit which includes a plurality of recursively connected boosting stages for generating a boosted output voltage to drive control gates via row decoder circuits and wordlines in an array of Flash EEPROM memory cells during a read mode of operation.
2. Description of the Prior Art
As is generally known in the area of memory devices and other semiconductor integrated circuits, there is often required voltages to be internally generated (on-chip) that are greater than an external or off-chip power supply potential which is supplied to it. For example, it is known that in Flash electrically erasable, programmable read-only memories (EEPROMs) a high voltage of approximately +5.0 volts is needed to be generated for the reading mode of operation of the Flash memory cells. As a result, such semiconductor memories will also typically include an internal voltage boosting circuit of some type for generating an output voltage which is boosted to be higher than an external power supply voltage.
One known prior art voltage boosting circuit for generating an on-chip voltage higher than the power supply potential utilizes a single bootstrapping stage which is responsive to a single pulse. In FIG. 1, there is shown a schematic circuit diagram of this prior art single stage voltage boosting circuit 10 for generating a boosted output voltage V.sub.OUT which is delivered via appropriate row decoder circuits 11 and wordlines WL0 . . . WLn to control gates in an array of Flash EEPROM memory cells.
The boosting circuit 10 includes a pre-charge portion 12 and a bootstrap portion 14. The pre-charge portion 12 is formed of a level-shifting CMOS inverter 16 and a P-channel pre-charge MOS transistor MPS1. The bootstrap portion 14 is formed of a P-channel MOS transistor MP1, an N-channel MOS transistor MN1, and a bootstrap capacitor C.sub.1. In addition, there is provided a CMOS inverter 18 and a load capacitor C.sub.S1. The input of the inverter 18 is connected to an input terminal 19 for receiving a single pulse BOOST of a predetermined duration. The load capacitor C.sub.S1 represents all of the stray or parasitic capacitances associated with the lead line 20 connected between the output node 22 and the ground potential VSS. The output node 22 is also connected to an output terminal 24 for providing the boosted output voltage V.sub.OUT.
In operation, when the input pulse BOOST is low the output voltage V.sub.OUT at the output terminal 24 will be precharged to the external power supply potential VDD since the P-channel precharge transistor MPS1 will be turned on. When the pulse BOOST makes a low-to-high transition, the precharge transistor MPS1 will be quickly turned off and the internal node A will also undergo a low-to-high transition of a magnitude equal to the off-chip power supply potential VDD. This will, in turn, cause the output voltage V.sub.OUT at the output terminal 24 to be raised or bootstrapped by the boost voltage V.sub.A at the internal node A via the bootstrap capacitor C1.
Since a fraction of the boost voltage V.sub.A is coupled to the output node 22 and is added to the initial precharged voltage V.sub.DD, the boosted output voltage V.sub.OUT can be calculated from the following equation: ##EQU1## where: EQU V.sub.DD =power supply potential VDD (2) EQU V.sub.A =input pulse peak VDD (3)
By substituting equations (2) and (3) into equation (1) and simplifying, there is given: ##EQU2##
From above equation (4), it can be seen that if the required maximum for the control gate voltage in the array of Flash memory cells is less than the level that can be generated by the boosting circuit 10 of FIG. 1, then the prior art boosting circuit 10 will be able to operate sufficiently. However, in view of the trend for deep-submicron CMOS technology of using a low power supply voltage (i.e., VDD is less than +2.0 volts), the prior art boosting circuit 10 will be unable to adequately supply sufficient control gate voltage for reading the memory cells in the Flash EEPROM memory array since the typical voltage required for reading is approximately +5.0 volts. Assuming that the capacitance value C.sub.1 is much greater than the capacitance value C.sub.S1, then V.sub.OUT is approximately +4.0 volts. Therefore, in a very low power supply voltage environment, additional means is needed for generating this high output voltage.
The inventor of the present invention has developed a simple and novel technique of utilizing the single stage boosting circuit of FIG. 1 so as to produce a boosted output voltage, which is significantly higher than what is traditionally available, for reading Flash EEPROM memory cells in a very low power supply voltage environment. This is achieved in the present invention by a voltage booster circuit which includes a plurality of recursively connected boosting stages for generating the boosted output voltage.